1. Field of the Invention
This invention relates to a layout and method to improve linearity and reduce voltage coefficient of resistance for resistors used in mixed-mode analog/digital applications.
2. Description of the Related Art
U.S. Pat. No. 6,103,622 to Huang describes a silicide process for mixed-mode analog digital/devices.
U.S. Pat. No. 5,924,011 to Huang describes a method for fabricating mixed analog/digital devices using a silicide process.
U.S. Pat. No. 6,054,359 to Tsui et al. describes a method for fabricating high sheet resistance polysilicon resistors.
U.S. Pat. No. 5,885,862 to Jao et al. describes a poly-load resistor for a static random access memory, SRAM, cell.
A paper entitled “Characterization of Polysilicon Resistors in Sub-0.25 μm CMOS USLI Applications” by Wen-Chau Liu, Member IEEE, Kong-Beng Thei, Hung-Ming Chuang, Kun-Wei Lin, Chin-Chuan Cheng, Yen-Shih Ho, Chi-Wen Su, Shyh-Chyi Wong, Chih-Hsien Lin, and Carlos H. Diaz, IEEE Electron Device Letters, Vol. 22, No. 7, pages 318–320, July 2001 describes characterization of polysilicon resistors.